NetFPGA Training School

The NetFPGA is an open source hardware and software platform designed for research and teaching. The need for high-speed and software programmable networks requires suitable hardware platforms for developing and testing novel network solutions. The increasing interest for the design of high-speed programmable dataplanes (such as the barefoot switches) also push toward the adoption of hardware prototype platforms where implement and verify dataplane architectures. Furthermore, the use of hybrid solutions in which FPGA and commodity servers represent another interesting research topic. In all these research fields, the NetFPGA platform is an ideal candidate prototype and develop efficient solutions. However, using NetFPGA can be difficult for network engineers that usually are not familiar with many of the hardware design concepts behind the development of FPGA systems. In this training school, we aim to show the main characteristics of the NetFPGA and some useful applications developed on top of it. Moreover, we will present the main concepts of FPGA based designs and we will run a series of labs exercise where the students will design,verify and implement on a SUME NetFPGA several hardware designs.

Location: The NetFPGA Training school was hosted at Telecom ParisTech and is sponsored by the NewNet@Paris Cisco’s Chair. The lessons were held at 46, Rue Barrault, Paris from July 3rd to July 6th.

Registration: The school is free of charge, but it is necessary to register by June 14th at the following link: registration

Teachers:  The teachers of the course will be Gianni Antichi, Senior Research Associate at the Computer Laboratory of the University of Cambridge and Salvatore Pontarelli, research associate at CNIT (Consorzio Nazionale Interuniversitario per le Telecomunicazioni) and visiting researcher at NewNet@Paris team.


The materia  used in this training school is available for download: [18MB]

[sha512sum: 135a33bbe6e8408b85738f7d325e30c420ea181fdd560f4ec91f825637a1f94afa1e64013adbd10bd110b70b0ad3c297fefb7d7f033c192b9382fac1dcc9f2c4]


Course schedule

First day (3-July-2017)


– Introduction

  • FPGA, HDL, state of the art

– NetFPGA Infrastructure

  • Life of a packet through the NetFPGA
  • Data plane
  • Control plane (registers/PCI interface)
  • Module Template
  • User Data Path

– FPGA Toolchain

  • Xilinx Vivado Design suite
  • Simulating NetFPGA on Vivado
  • Implementing/download NetFPGA firmware using Vivado


– ONST Traffic Generator

  • Architecture
  • Features
  • Future work

– Verilog HDL 1

  • combinatorial blocks
  • sequential blocks
  • module instantiation

– Lab. 1

  • Getting started with NetFPGA: programming the board, sending/receiving packets, reading stats, configure interfaces

Second day (4-July-2017)


– Verilog HDL 2

  • Operators, data types
  • Arithmetic operations
  • Registers, memories

– Lab. 2:

  • Design  of a block computing IP CHKSUM
  • NetFPGA Simulation


– Verilog HDL 3

  • Initial statement, always statement
  • blocking/non-blocking assignment
  • loops

– Lab. 3

  • Design and simulation of a finite state machine (port knocking) in Verilog
  • NetFPGA Simulation

Third day (5-July-2017)  


– Lab. 4

  • Design of a block providing programmable load balancer
  • Software/Hardware integration
  • NetFPGA Simulation
  • Build Hardware


– Lab. 4

  • Hardware Test
  • Hardware Debug via pre-compiled registers
  • Hardware Debug via Integrated Logic Analyzer